Evaluation of Switch-to-Switch Header Flit Protection Schemes in Networks-on-Chip

Signal integrity and packet data protection against soft errors represent highly relevant challenges for Networks-on-Chip regarding the shrinking of process technology. Therefore, data protection and error recovery strategies at the End-to-End level are the most convenient solutions considering overall implementation costs and performance penalties. Nevertheless, protection of packet header control information at the data link layer is indispensable, since the header contains data highly relevant for correct routing. Corrupted data by the presence of soft errors may lead to misdirected packets affecting latency, data misinterpretation due to corrupted encoding flags or loss of the packet. Thus, additional Switch-to-Switch header protection is inevitable. By using error correcting and detecting codes the number of additional components of a Network-on-Chip router can grow inappropriately. Accordingly we considered different techniques like resource sharing and minimizing the number of decoders. In this work we evaluate several concepts by means of simulations and syntheses utilizing a 45 nm process technology. Our results show that header protection can be applied with very low performance degradation under minimal additional hardware costs by gaining a very reliable header flit.